6 5 $ 0 copyright ?1998 alliance semiconductor. all rights reserved. ? $ 6 & $ 6 & / $ 6 & $ 6 & / ', ',' ' % % $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 . e & 0 2 66 5 $ 0 & r pp r q , 2 i d p l o \ )hdwxuhv ? organization: 131,072 words 8 bits ? high speed - 10/12/15/20 ns address access time - 3/3/4/5 ns output enable access time ? low power consumption available - active: 180 mw max (3v, 15 ns) - standby: 1.8 mw max, cmos i/o - very low dc component in active power ? 2.0v data retention ? equal access and cycle times ? easy memory expansion with ce1 , ce2, oe inputs ? ttl/lvttl-compatible, three-state i/o ? 32-pin jedec standard packages - 300 mil pdip and soj socket compatible with 7c512 (64k8) - 400 mil soj - 8mm 20mm tsop ? esd protection 3 2000 volts ? latch-up current 3 200 ma ? 3.3v and 5.0v versions available ? industrial and commercial temperature available ? intelliwatt tm low power and cpg versions available /rjlfeorfngldjudp 512 256 8 array (1,048,576) sense amp input buffer a10 a11 a12 a13 a14 a15 a16 i/o0 i/o7 oe ce1 we column decoder row decoder control circuit a9 a0 a1 a2 a3 a4 a5 a6 a7 vcc gnd a8 ce2 3lqduudqjhphqw 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc a15 ce2 we a13 a8 a9 a11 oe a10 ce1 i/o7 i/o6 i/o5 i/o4 i/o3 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd dip, soj vcc a15 ce2 we a13 a8 a9 a11 oe a10 ce1 i/o7 i/o6 i/o4 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 tsop i/o2 gnd i/o5 i/o3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 31 30 29 28 27 26 25 24 23 22 21 20 19 15 16 18 17 6hohfwlrqjxlgh shaded areas contain advance information. -10 -12 -15 -20 unit maximum address access time 10 12 15 20 ns maximum output enable access time 3345ns maximum operating current as7c1024 175 160 120 110 ma as7c1024l C 120 95 80 ma as7c31024 150 100 70 65 ma as7c31024l C 605045ma maximum static standby current (l) 0.1 0.1 0.1 0.1 ma
6 5 $ 0 $ 6 & i d p l o \ ? $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ',' ',' % % )xqfwlrqdoghvfulswlrq the as7c1024 and as7c31024 are high performance cmos 1,048,576-bit static random access memories (sram) organized as 131,072 words 8 bits. it is designed for memory applications where fast data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 10/12/15/20 ns with output enable access times (t oe ) of 3/3/4/5 ns are ideal for high performance applications. active high and low chip enables (ce1 , ce2) permit easy memory expansion with multiple-bank systems. when ce1 is high or ce2 is low the device enters standby mode. if inputs are still toggling, the devices will consume i sb power. if the bus is static, then full standby power is reached (i sb1 or i sb2 ). the 31024l for example, is guaranteed not to exceed 0.33mw under nominal full standby conditions. all devices in this family will retain data when v cc is reduced as low as 2.0v. a write cycle is accomplished by asserting write enable (we ) and both chip enables (ce1 , ce2). data on the input pins i/o0-i/o7 is written on the rising edge of we (write cycle 1) or the active-to-inactive edge of ce1 or ce2 (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and both chip enables (ce1 , ce2), with write enable (we ) high. the chip drives i/o pins with the data word referenced by the input address. when either chip enable is inactive, output enable is inact ive, or write enable is active, output drivers stay in high-impedance mode. all chip inputs and outputs are ttl/lvttl-compatible, and operation is from a single 5v supply or 3.3v supply. 128kx8 and 64kx1 6 srams are also available in ultra-low power intelliwatt tm versions. for intelliwatt specifications, please see the as7c31024ll and as7c31026ll datasheets respectively. the revolutionary pinout (cpg) version of the 128kx8 may be found as as7c1025, as7c31025. $evroxwhpd[lpxpudwlqjv stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute max- imum rating conditions for extended periods may affect reliability. 7uxwkwdeoh key: x = dont care, l = low, h = high parameter symbol min max unit voltage on any pin relative to gnd v t C0.5 +7.0 v power dissipation p d C1.0w storage temperature (plastic) t stg C55 +150 o c temperature under bias t bias C10 +85 o c dc output current i out C20ma ce1 ce2 we oe data mode hxxxhigh z standby (i sb , i sb1 ) xl xxhigh z standby (i sb , i sb1 ) l hhhhigh z output disable l hhl d out read lhlxd in write
6 5 $ 0 ? $ 6 & i d p l o \ ' ', ,' ' % % $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 6 5 $ 0 5hfrpphqghgrshudwlqjfrqglwlrqv ? v il min = C3.0v for pulse width less than t rc /2. '&lqsxwrxwsxwfkdudfwhulvwlfv$6&idplo\ 1 shaded areas contain advance information. 3rzhuvxsso\fkdudfwhulvwlfv$6&dqg$6&/ 1 shaded areas contain advance information. parameter symbol min nominal max unit supply voltage 5v devices v cc 4.55.05.5v 3.3v devices v cc 3.03.33.6v gnd 0.0 0.0 0.0 v input voltage as7c1024 v ih 2.2 C v cc + 0.5 v as7c31024 v ih 2.0 C v cc + 0.5 v v il ? C0.5 C 0.8 v parameter symbol test conditions -10 -12 -15 -20 unit min max min max min max min max input leakage current | i li | v cc = max, v in = gnd to v cc C 1C1C1C1 m a output leakage current | i lo | ce1 = v ih or ce2 = v il , v cc = max, v out = gnd to v cc C 1C1C1C1 m a output voltage v ol i ol = 8 ma, v cc = min C 0.4C0.4C0.4C0.4v v oh i oh = C4 ma, v cc = min 2.4 C2.4C2.4C2.4C v parameter symbol test conditions -10 -12 -15 -20 unit min max min max min max min max operating power supply current i cc ce1 = v il , ce2 = v ih , f = f max, i out = 0 ma C 175 C 160 C 120 C 110 ma l C CC120C95C80ma standby power supply current i sb ce1 = v ih or ce2 = v il , f = f max , all inputs toggling C 55 C 50 C 40 C 40 ma l C C C 35 C 25 C 25 ma i sb1 chip disabled, f = 0, v in 0.2v or v in 3 v cc C0.2v C 5C5C5C5ma l C C C 0.5 C 0.5 C 0.5 ma i sb2 chip disabled, f = 0,t a = 25c v in 0.2v or v in 3 v cc C0.2v, l C C C 0.1 C 0.1 C 0.1 ma
6 5 $ 0 $ 6 & i d p l o \ ? $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ',' ',' % % 3rzhuvxsso\fkdudfwhulvwlfv$6&dqg$6&/ 1 shaded areas contain advance information. &dsdflwdqfh 2 i 0+]7 d 5rrpwhpshudwxuh9 && 9 5hdgf\foh 3,9,12 parameter symbol test conditions -10 -12 -15 -20 unit min max min max min max min max operating power supply current i cc ce1 = v il , ce2 = v ih , f = f max, i out = 0 ma C 150 C 100 C 70 C 65 ma l C C C 60 C 50 C 45 ma standby power supply current i sb ce1 = v ih or ce2 = v il , f = f max C 55 C 50 C 40 C 40 ma l C C C 35 C 25 C 25 ma i sb1 chip disabled, f = 0, v in 0.2v or v in 3 v cc C0.2v C 5C5C5C5ma l C C C 0.5 C 0.5 C 0.5 ma i sb2 chip disabled, f = 0,t a = 25c v in 0.2v or v in 3 v cc C0.2v, l C C C 0.1 C 0.1 C 0.1 ma parameter symbol signals test conditions max unit input capacitance c in a, ce1 , ce2, we , oe v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf parameter symbol -10 -12 -15 -20 unit notes min max min max min max min max read cycle time t rc 10 C 12 C 15 C 20 C ns address access time t aa C 10 C 12 C 15 C 20 ns 3 chip enable (ce1 ) access time t ace1 C 10 C 12 C 15 C 20 ns 3, 12 chip enable (ce2) access time t ace2 C 10 C 12 C 15 C 20 ns 3, 12 output enable (oe ) access time t oe C 3C3C4C5 ns output hold from address change t oh 2 C3C3C3C ns 5 ce1 low to output in low z t clz1 3 C3C3C3C ns4, 5, 12 ce2 high to output in low z t clz2 3 C3C3C3C ns4, 5, 12 ce1 high to output in high z t chz1 C 3C3C4C5 ns4, 5, 12 ce2 low to output in high z t chz2 C 3C3C4C5 ns4, 5, 12 oe low to output in low z t olz 0 C0C0C0C ns 4, 5 oe high to output in high z t ohz C 3C3C4C5 ns 4, 5 power up time t pu 0 C0C0C0C ns4, 5, 12 power down time t pd C 10 C 12 C 15 C 20 ns 4, 5, 12
6 5 $ 0 ? $ 6 & i d p l o \ ' ', ,' ' % % $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 6 5 $ 0 .h\wrvzlwfklqjzdyhirupv 5hdgzdyhirup 3,6,7,9,12 $gguhvvfrqwuroohg 5hdgzdyhirup 3,6,8,9,12 &( dqg&(frqwuroohg undefined output/dont care falling input rising input address d out data valid t oh t aa t rc supply current ce2 oe d out t oe t olz t ace1, t ace2 t chz1, t chz2 t clz1, tclz2 t pu t pd i cc i sb 50% 50% d ata valid t rc 1 ce1 t ohz
6 5 $ 0 $ 6 & i d p l o \ ? $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ',' ',' % % :ulwhf\foh 11, 12 shaded areas contain advance information. :ulwhzdyhirup 10,11,12 :( frqwuroohg :ulwhzdyhirup 10,11,12 &( dqg&(frqwuroohg parameter symbol -10 -12 -15 -20 unit notes min max min max min max min max write cycle time t wc 10 C 12 C 15 C 20 C ns chip enable (ce1 ) to write end t cw1 9 C 10 C 12 C 12 C ns 12 chip enable (ce2) to write end t cw2 9 C 10 C 12 C 12 C ns 12 address setup to write end t aw 9 C 10 C 12 C 12 C ns address setup time t as 0 C0C0C0C ns 12 write pulse width t wp 7 C8C9C12C ns address hold from end of write t ah 0 C0C0C0C ns data valid to write end t dw 6 C6C9C10C ns data hold time t dh 0 C 0 C 0 C 0 C ns 4, 5 write enable to output in high z t wz C 5 C 5 C 5 C 5 ns 4, 5 output active from write end t ow 3 C 3 C 3 C 3 C ns 4, 5 t aw t ah t wc address we d out t dh t ow t dw t wz t wp t as data valid d in t aw address ce1 we d out t cw1, t cw2 t wp t dw t dh t ah t wz t wc t as ce2 data valid d in
6 5 $ 0 ? $ 6 & i d p l o \ ' ', ,' ' % % $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 6 5 $ 0 'dwduhwhqwlrqfkdudfwhulvwlfv 14 'dwduhwhqwlrqzdyhirup $&whvwfrqglwlrqv parameter symbol test conditions min max unit v cc for data retention v dr v cc = 2.0v ce1 3 v cc C0.2v or ce2 0.2v v in 3 v cc C0.2v or v in 0.2v 2.0 C v data retention current i ccdr C 500 (100 l) a chip deselect to data retention time t cdr 0Cns operation recovery time t r t rc Cns input leakage current | i li | C1a v cc ce t r t cdr data retention mode 4.5v or 2.7v 4.5v or 2.7v v dr 3 2.0v v ih v ih v dr 255 w C 5v output load: see figure b, except as noted see figure c. C 3.3v output load: see figure d, except as noted see figure e. C input pulse level: gnd to 3.0v. see figure a. C input rise and fall times: 5 ns. see figure a. C input and output timing reference levels: 1.5v. 5 pf* 480 w d out gnd +5v 168 w thevenin equivalent: d out +1.728v figure c: output load for t clz , t chz , t olz , t ohz , t ow 255 w 30 pf* 480 w d out gnd +5v figure b: output load *including scope 10% 90% 10% 90% gnd +3.0v figure a: input waveform and jig capacitance 350 w 5 pf* 320 w d out gnd +3.3v 350 w 30 pf* 320 w d out gnd +3.3v figure d: output load *including scope and jig capacitance figure c: output load for t clz , t chz , t olz , t ohz , t ow
6 5 $ 0 $ 6 & i d p l o \ ? $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ',' ',' % % 7\slfdo'&dqg$&fkdudfwhulvwlfv supply voltage (v) 4.0 5.5 6.0 5.0 4.5 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb ambient temperature (c) C55 80 125 35 C10 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb vs. ambient temperature t a vs. supply voltage v cc ambient temperature (c) -55 80 125 35 -10 0.2 1 0.04 5 25 625 normalized i sb1 (log scale) normalized supply current i sb1 vs. ambient temperature t a supply voltage (v) 4.0 5.5 6.0 5.0 4.5 0.6 0.7 0.9 1.0 0.8 1.1 1.2 1.3 normalized access time normalized access time t aa ambient temperature (c) C55 80 125 35 C10 0.6 0.7 0.9 1.0 0.8 1.1 1.2 1.3 normalized access time normalized access time t aa cycle frequency (mhz) 0 1/t rc 1/(2t rc ) 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc normalized supply current i cc vs. ambient temperature t a vs. cycle frequency vs. supply voltage v cc t a = 25c output voltage (v) 0.0 3.75 5.0 2.5 1.25 0 20 60 80 40 100 120 140 output source current (ma) output source current i oh output voltage (v) 0.0 3.75 5.0 2.5 1.25 output sink current (ma) output sink current i ol vs. output voltage v ol vs. output voltage v oh 0 20 60 80 40 100 120 140 v cc = 5.0v t a = 25c v cc = 5.0v t a = 25c capacitance (pf) 0750 1000 500 250 0 5 15 20 10 25 30 35 change in t aa (ns) typical access time change d t aa vs. output capacitive loading
6 5 $ 0 ? $ 6 & i d p l o \ ' ', ,' ' % % $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 6 5 $ 0 1rwhv 1 during v cc power-up, a pull-up resistor to v cc on ce1 is required to meet i sb specification. 2 this parameter is sampled and not 100% tested. 3 for test conditions, see ac test conditions , figures a, b, c. 4t clz and t chz are specified with cl = 5pf as in figure c. transition is measured 500mv from steady-state voltage. 5 this parameter is guaranteed but not tested. 6we is high for read cycle. 7ce1 and oe are low and ce2 is high for read cycle. 8 address valid prior to or coincident with ce transition low. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 ce1 or we must be high or ce2 low during address transitions. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. 12 ce1 and ce2 have identical timing. 13 this data applicable to the as7c1024. the as7c31024 functions similarly. 14 2v data retention applies to commercial temperature operating range only. $6&idplo\rughulqjfrghv shaded areas contain advance information. $6&idplo\sduwqxpehulqjv\vwhp package \ access time 10 ns 12 ns 15 ns 20 ns plastic dip, 300 mil new designs using pdip are discouraged. contact alliance sales for pdip availability of limited production. plastic soj, 300 mil as7c1024-10tjc as7c1024-12tjc as7c1024-15tjc as7c1024-20tjc as7c1024l-12tjc as7c1024l-15tjc as7c1024l-20tjc as7c31024-10tjc as7c31024-12tjc as7c31024-15tjc as7c31024-15tji as7c31024-20tjc as7c31024-20tji as7c31024l-12tjc as7c31024l-15tjc as7c31024l-20tjc plastic soj, 400 mil as7c1024-10jc as7c1024-12jc as7c1024-15jc as7c1024-15ji as7c1024-20jc as7c1024-20ji as7c1024l-12jc as7c1024l-15jc as7c1024l-20jc as7c31024-10jc as7c31024-12jc as7c31024-15jc as7c31024-15ji as7c31024-20jc as7c31024-20ji as7c31024l-12jc as7c31024l-15jc as7c31024l-20jc tsop 820 as7c1024-12tc as7c1024-15tc as7c1024-20tc AS7C1024L-12TC as7c1024l-15tc as7c1024l-20tc as7c31024-12tc as7c31024-15tc as7c31024-20tc as7c31024l-12tc as7c31024l-15tc as7c31024l-20tc as7c x 1024 x Cxx x x sram prefix blank=5v cmos 3=3.3v cmos device number l = low power access time package:tp =pdip 300 mil t =tsop 820 j =soj 400 mil tj =soj 300 mil temperature range c = commercial, 0c to 70c i = industrial, -40c to 85c
6 5 $ 0 $ 6 & i d p l o \ ? $ // , $ 1 & ( 6 ( 0 , & 2 1 ' 8 & 7 2 5 ',' ',' % %
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